1. Field of the Invention
This invention relates to a semiconductor device, specifically to an LDMOS transistor that has an excellent ESD tolerance.
2. Description of the Related Art
The LDMOS transistor, as well as an IGBT, is widely used in a switching power supply such as a DC-DC converter, an inverter circuit of lighting apparatus, an inverter circuit for a motor and the like, because it is excellent in high current drivability, high withstand voltage and switching characteristics, and is easy to use compared with a bipolar type power transistor. The LDMOS is an acronym for Lateral Double Diffusion Metal Oxide Semiconductor. And the ESD is an acronym for Electro-Static Discharge.
A simplified cross-sectional view of the LDMOS transistor is shown in FIG. 12B, for example. The LDMOS transistor shown in FIG. 12B is structured as an N channel MOS transistor. It is composed of an N type semiconductor layer 51, an N− type drift layer 52, an N+ type drain layer 57, a P type base layer 53, an N+ type source layer 56, a P+ type contact layer 58, a gate insulation film 54 and a gate electrode 55. FIG. 12A shows a structure formed by removing the P+ type contact layer 58 from the structure shown in FIG. 12B. Considering the operations of the LDMOS transistor, the structure shown in FIG. 12A having no P+ type contact layer 58 seems to be sufficient.
However, following problem is caused with the LDMOS transistor having no P+ type contact layer 58 as shown in FIG. 12A, when the LDMOS transistor is turned on by applying a positive high voltage +Vd to the N+ type drain layer 57, grounding the N+ type source layer 56, and applying a positive voltage to the gate electrode 55. The problem is that a parasitic NPN transistor, which is composed of an emitter made of the N+ type source layer 56, a base made of the P type base layer 53 and a collector made of the N+ type drain layer 57 and the like, is turned on by the reason to be described below to increase an unnecessary current that can be not controlled by the gate electrode 55, when the LDMOS transistor is turned on and an electron current flows from the N+ type source layer 56 to the N+ type drain layer 57.
When the LDMOS transistor is turned on, electrons flow out of the N+ type source layer 56 into the N− type drift layer 52 through a channel layer, are accelerated by a high electric field in the N− type drift layer 52, and flow into the N+ type drain layer 57. In this case, electrons accelerated in the N− type drift layer 52 are turned into hot electrons having high energy, and interact with lattices and the like in the N− type drift layer 52 to generate a large number of electron-hole pairs. In FIG. 12A, a circled e− represents the hot electron, and e− and e+ represent the electron-hole pair generated by the interaction with the hot electron.
While the electrons generated as described above flow into the N+ type drain layer 57, the holes flow toward the N+ type source layer 56 at the ground electric potential. The holes that reached the N+ type source layer 56 are blocked by its potential bather and remain dispersed in the P type base layer 53 around the N+ type source layer 56, so that an electric potential at the P type base layer 53 becomes higher than the electric potential at the N+ type source layer 56.
As a result, the parasitic NPN transistor, which is composed of the emitter made of the N+ type source layer 56, the base made of the P type base layer 53 and the collector made of the N+ type drain layer 57, is turned on and the electron current flows out of the N+ type source layer 56 to the P type base layer 53, since the electric potential at the P type base layer 53 that makes the base layer becomes higher than the electric potential at the N+ type source layer 56 that makes the emitter layer. The electron current that has flown into the P type base layer 53 further flows into the N+ type drain layer 57 at the positive voltage +Vd. As a result, there is caused the problem that the unnecessary current which can be not controlled by the gate electrode 55 is increased.
In the case where the P+ type contact layer 58 is formed in parallel with the N+ type source layer 56 and extending into the P type base layer 53 as shown in FIG. 12B, on the other hand, the structure is impervious to the problem that the parasitic NPN transistor is turned on. The electron-hole pairs are generated in the N− type drain layer 52 by the hot electrons and the electrons flow into the N+ type drain layer 57 as in the case of the structure shown in FIG. 12A. However, there is a difference regarding the holes.
Unlike in the structure shown in FIG. 12A, most of holes flowing toward the N+ type source layer 56 at the ground electric potential flow into the P+ type contact layer 58 formed in parallel with the N+ type source layer 56 and extending into the P type base layer 53. That is because the P+ type contact layer 58 does not make the potential barrier against the holes. Therefore, a difference between the electric potential at the N+ type source layer 56 and the electric potential at the P type base layer 53 adjacent the N+ type source layer 56 is decreased to reduce a possibility that the parasitic NPN transistor described above would be turned on.
However, if the parasitic NPN transistor would be not turned on, a dielectric breakdown between the source and the drain would be caused to destroy the LDMOS transistor when a large positive surge voltage due to an ESD extremely larger than a normal power supply voltage is applied to the N+ type drain layer 57. The problem and its countermeasure in the case where the large positive surge voltage due to the ESD is applied to the N+ type drain layer 57 are disclosed in Japanese Patent Application Publication No. 2001-320047.
When the large positive surge voltage due to the ESD is applied to the N+ type drain layer 57, an avalanche breakdown occurs in the vicinity of the N+ type drain layer 57 under a strong electric field so that a large number of electron-hole pairs are generated. The generated electrons flow into the N+ type drain layer 57, while the generated holes flow into the P type base layer 53.
The electric potential at the P type base layer 53 is raised above the electric potential at the N+ type source layer 56 by the holes that flow into the P type base layer 53. As a result, the parasitic NPN transistor, which is composed of the emitter made of the N+ type source layer 56, the base made of the P type base layer 53 and the collector made of the N+ type drain layer 57 and the like, is turned on.
A voltage between the N+ type source layer 56 and the N+ type drain layer 57 is clamped at a low voltage and the destruction of the device due to the ESD is prevented by the turning on of the parasitic NPN transistor. However, a localized current convergence occurs in the vicinity of the N+ type drain layer 57 to cause a thermal runaway in this region.
Thus, sufficient ESD tolerance is not obtained and there is caused a problem in extreme cases that the vicinity of the N+ type drain layer 57 is destroyed. There is disclosed that an LDMOS transistor with an improved ESD tolerance is realized by forming a P+ type anode layer (not shown) adjacent the N+ type drain layer 57.
In the same Japanese publication, the insufficient ESD tolerance is attributed to the thermal runaway due to the localized convergence of the avalanche current in the vicinity of the N+ type drain layer 57, and its countermeasure is modification in the drain-side structure. It is taken for granted that the parasitic NPN transistor is turned on. However, the P+ type contact layer 58 also serves to prevent the parasitic NPN transistor from turning on.
Therefore, it is necessary that the parasitic transistor is turned on when the abnormally large surge voltage is applied, while the parasitic NPN transistor is prevented from turning on in the normal operation. The inventors investigated how the P+ type contact layer 58 and the N+ type source layer 56 should be structured to meet the requirements described above.